1. Technical Field
The present invention relates to a test wafer unit and a test system. In particular, the present invention relates to a test wafer unit and a test system for testing a plurality of semiconductor chips formed on a semiconductor wafer.
2. Related Art
An apparatus is already known to conduct a test to a semiconductor wafer in which a plurality of semiconductor chips are formed to test pass/fail of each semiconductor chip (see Japanese Patent Application Publication No. 2002-222839 for example). Such an apparatus can have a probe card that can be collectively electrically connected to a plurality of semiconductor chips.
Generally, a probe card is formed using a printed circuit board or the like. A plurality of probe pins formed on the printed circuit board can be collectively electrically connected to the plurality of semiconductor chips.
One method of testing a semiconductor chip uses a BOST circuit. The BOST circuit can be mounted on a probe card. When a test is conducted to a semiconductor wafer, however, a multitude of BOST circuits are required, which are difficult to be implemented on the printed circuit board of the probe card.
Another method of testing a semiconductor chip uses a BIST circuit provided in a semiconductor chip. However, this method involves formation of circuits, in the semiconductor chip, not used in the actual operation, thereby reducing the region for forming the actually operating circuits in the semiconductor chip.
If a semiconductor chip is tested as mounted on a semiconductor wafer, the area on which the test circuits are mountable decreases if the mounting density of the semiconductor chips is large. This makes it occasionally difficult to mount highly advanced test circuits.